1. Field of the Invention
The present invention relates to the field of integrated circuits; more specifically, it relates to the design and verification of power distribution networks in integrated circuit chips containing voltage islands.
2. Background of the Invention
Integrated circuit (IC) chip design and manufacturing techniques have progressed to the point where advanced levels of system-on-chip (SOC) integration complexity create serious problems related to the distribution of power to the integrated circuit. Such problems are associated with battery life, and the thermal and electrical integrity and robustness of on-chip interconnect.
A broad set of techniques for reducing the power required by IC chips includes partitioning the individual circuits into functional blocks that may be selectively powered up or down or even powered at voltage levels that are different from chip-level voltages. Circuits that may be periodically powered down, or run at different voltage levels, or at voltage levels derived from separate sources, are isolated from the primary power distribution network of the IC chip by placing them in xe2x80x9cvoltage islands.xe2x80x9d The power distribution network of each voltage island derives power from the primary, chip-level power distribution network using voltage translation interface (VTI) circuits. Included in the class of VTI circuits are series-connected VDDx switches (i.e., headers), series-connected GNDx switches (i.e., footers), level shifters, voltage regulators, DC-to-DC converters, and even direct electrical connections (i.e., wires).
An IC power distribution network may comprise one or more of chip-level networks, each powered by arbitrary voltage level pairs, for example, VDD1 and GND1, VDD2 and GND2, etc. Moreover, a single supply voltage level may be shared among a multiplicity of chip-level networks, for example, VDD1 and GND, VDD2 and GND, etc.
Power distribution analysis for detecting power xe2x80x9chot spotsxe2x80x9d and other potential reliability problems in IC chip design is critical to the success of any integrated design and manufacturing operation.
Traditional methods of power distribution analysis use circuit simulation and linear network models of the chip power distribution to determine the currents and voltages associated with power grid wires and network nodes, respectively.
In the linear model, each network node represents the intersection of power grid wires on adjacent metallization levels, the location of a power source (e.g., C4 or wirebond pad), or the location of an active device or circuit. Of particular interest for voltage analysis are the subset of network nodes called xe2x80x9cports,xe2x80x9d which represent the modeled locations where active circuits are connected to the power distribution network.
Traditional analysis methods treat IC power distribution systems as passive resistive-inductive-capacitive (RLC) networks and determine current and voltage values by circuit simulation, where current sources are used to model the switching behavior of the active circuits. Moreover, since typical power distribution models contain millions of nodes, the relative efficiency of xe2x80x9clinearxe2x80x9d circuit simulation has made it essential for this type of analysis.
Further, traditional methods cannot be directly applied to IC chips containing voltage islands for at least two reasons. First, VTI circuits, in general, disrupt the electrical continuity of the power distribution system and its modeled RLC network equivalent. Second, the VTI circuits are generally characterized by nonlinear current-voltage relationships and thus difficult, or impossible, to efficiently model for linear circuit simulation.
Therefore, a need exists for an efficient method of analyzing power distributions in IC chips containing voltage islands.
A first aspect of the present invention is a method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.
A second aspect of the present invention is method of analyzing power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network is connected to a chip-level power distribution network by one or more voltage translation interface circuits comprising: (a) creating a chip-level power distribution network model connected to chip-level placed circuits modeled as current sources; (b) independently creating a voltage-island power distribution network model connected between voltage translation interface circuit outputs and voltage-island placed circuits modeled as current sources; (c) obtaining voltage translation interface circuit currents by: (i) in a first iteration, using the ideal value of an external voltage source voltage as the values of the voltage translation interface circuit output voltages; (ii) in subsequent iterations using the most recently computed values for the voltage translation interface circuit output voltages; and (iii) simulating the voltage-island power distribution network model with its corresponding voltage-island placed circuits modeled as current sources and the most recently obtained values for its voltage translation interface circuit output voltages applied as voltage sources; (d) exciting the chip-level power distribution network model with the most recently obtained values of the voltage translation interface circuit currents; (e) obtaining, through simulation of the chip-level power distribution network model, values for the voltage translation interface circuit input voltages and values for the chip-level placed circuit port voltages; (f) calculating updated values for the voltage translation interface circuit output voltages, based on the most recently obtained values for the voltage translation interface circuit input voltages, the currents through the voltage translation interface circuits, and the current-voltage characteristics of the voltage translation interface circuits; and (g) comparing the updated values to immediately previous values for the chip-level placed circuit port voltages, voltage translation interface circuit input voltages, and voltage translation circuit output voltages, and, if not converged to within a preset limit, repeating steps (c) through (g).
A third aspect of the present invention is a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for analyzing power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network is connected to a chip-level power distribution network by one or more voltage translation interface circuits, the method steps comprising: (a) creating a chip-level power distribution network model connected to chip-level placed circuits modeled as current sources; (b) independently creating a voltage-island power distribution network model connected between voltage translation interface circuit outputs and voltage-island placed circuits modeled as current sources; (c) obtaining voltage translation interface circuit currents by: (i) in a first iteration, using the ideal value of an external voltage source voltage as the values of the voltage translation interface circuit output voltages; (ii) in subsequent iterations using the most recently computed values for the voltage translation interface circuit output voltages; and (iii) simulating the voltage-island power distribution network model with its corresponding voltage-island placed circuits modeled as current sources and the most recently obtained values for its voltage translation interface circuit output voltages applied as voltage sources; (d) exciting the chip-level power distribution network model with the most recently obtained values of the voltage translation interface circuit currents; (e) obtaining, through simulation of the chip-level power distribution network model, values for the voltage translation interface circuit input voltages and values for the chip-level placed circuit port voltages; (f) calculating updated values for the voltage translation interface circuit output voltages, based on the most recently obtained values for the voltage translation interface circuit input voltages, the currents through the voltage translation interface circuits, and the current-voltage characteristics of the voltage translation interface circuits; and (g) comparing the updated values to immediately previous values for the chip-level placed circuit port voltages, voltage translation interface circuit input voltages, and voltage translation circuit output voltages, and, if not converged to within a preset limit, repeating steps (c) through (g).
A fourth aspect of the present invention is a computer system comprising a processor, an address/data bus coupled to the processor, and a computer-readable memory unit coupled to communicate with the processor, the memory unit containing instructions that when executed implement a method for analyzing power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits, the method comprising the computer implemented steps of: (a) creating a chip-level power distribution network model connected to chip-level placed circuits modeled as current sources; (b) independently creating a voltage-island power distribution network model connected between voltage translation interface circuit outputs and voltage-island placed circuits modeled as current sources; (c) obtaining voltage translation interface circuit currents by: (i) in a first iteration, using the ideal value of an external voltage source voltage as the values of the voltage translation interface circuit output voltages; (ii) in subsequent iterations using the most recently computed values for the voltage translation interface circuit output voltages; and (iii) simulating the voltage-island power distribution network model with its corresponding voltage-island placed circuits modeled as current sources and the most recently obtained values for its voltage translation interface circuit output voltages applied as voltage sources; (d) exciting the chip-level power distribution network model with the most recently obtained values of the voltage translation interface circuit currents; (e) obtaining, through simulation of the chip-level power distribution network model, values for the voltage translation interface circuit input voltages and values for the chip-level placed circuit port voltages; (f) calculating updated values for the voltage translation interface circuit output voltages, based on the most recently obtained values for the voltage translation interface circuit input voltages, the currents through the voltage translation interface circuits, and the current-voltage characteristics of the voltage translation interface circuits; and (g) comparing the updated values to immediately previous values for the chip-level placed circuit port voltages, voltage translation interface circuit input voltages, and voltage translation circuit output voltages, and, if not converged to within a preset limit, repeating steps (c) through (g).